In recent years, higher integration and surface mounting of electronic devices are employed from year to year in market trends toward making electronic equipment smaller, lighter, and highly functioning. For example, making semiconductor devices higher in pin count and thinner is approaching a limit in conventional surface-mounting semiconductor devices, represented by Quad Flat Packages (QFPs) and Small Outline Packages (SOPs), while in order to address need for making them further higher in pin count and thinner, area mounting semiconductor devices such as Lead Frame-Chip Scale Packages (LF-CSPs) and Ball Grid Arrays (BGAs) have been newly developed as next-generation semiconductor devices (Patent Literature 1).
Area mounting semiconductor devices are fabricated in the following steps. First, a semiconductor chip is mounted on one side of a metal or organic substrate by using a die attach paste or the like, and the substrate surface having the semiconductor chip mounted thereon, that is, only one surface of the substrate, is subjected to molding and encapsulation using an epoxy resin composition or the like. After that, the surface of the substrate on which no semiconductor chips have been mounted is subjected to a process in which bump electrodes (solder balls) are attached thereto (a reflow process). Further, a process is carried out in which area mounting semiconductor devices of this type are mounted on a mother board (a secondary mounting process), thereby leading to the production of electronic equipment. Area mounting semiconductor devices are thinner, as compared to conventional packages in which each surface of a substrate is subjected to encapsulation, and thus tend to have a greater warpage resulting from differences in coefficient of thermal expansion between component materials, and often suffer a problem that causes detachment and cracking to occur during reflowing.
In addition, removing and eliminating any lead component from solders which are used in mounting electronic devices on substrates is in progress as part of being environmentally friendly. As a solder containing no lead component (hereinafter referred to as a lead-free solder), Sn—Ag—Cu solders (having a melting point of about 220° C.), recommended by the Japan Electronics and Information Technology Industries Association (JEITA) are widely used. However, since these solders have higher melting points, relative to conventional Sn—Pd solders (having a melting point of about 200° C.), there has become more apparent a problem that no junctions are formed due to warpage of the package during mounting of electronic devices as described above. For this reason, the inhibition of package warpage against the rise in the melting temperature of solders has been required more and more for thermosetting adhesive compositions which are employed for adhering semiconductor chips onto circuit boards and others. Furthermore, a reflow process at high temperatures will increase internal stress of a package, and thus will be prone to cause detachment and eventually cracks in the inside of a semiconductor product during the reflow process.
Also for outer platings of semiconductor products, there have been increasing cases where a plating on lead frames is changed to a nickel-palladium plating for the purpose of being lead-free. In the case of nickel-palladium platings, a thin gold plating (gold flashing) is applied with the purpose of improving the stability of the surface Pd layer. However, the smoothness of the nickel-palladium plating itself and the presence of gold result in reduced adhesion force, as compared with usual silver-plated copper frames and others. Reduction of adhesion force will cause detachment and cracks in the inside of a semiconductor product during reflowing.
In order to inhibit package warpage, for example, there has been proposed a method which employs an encapsulating resin with a low coefficient of thermal expansion (Patent Literature 2). In addition, in order to suppress detachment, there have been also presented, for example, a method in which a die pad is formed into a structure that is satisfactory in physical adhesiveness with a encapsulating resin, thereby improving the adhesion strength between the die pad and the encapsulating resin (Patent Literature 3), and a method in which the glass transition point (Tg) of an encapsulating resin is increased, so as to reduce its elastic modulus at high temperatures (Patent Literature 4). There has also been proposed a method which utilizes copolymerization of two different functional groups, thereby achieving a balance between low stress and adhesion of an adhesive (Patent Literature 5). By using only these methods, however, sufficient solutions cannot be provided for failures that are caused in the above-described semiconductor devices.
Thus, there is a desire for a material which is superior in adhesion and low stress and capable of decreasing the warpage of semiconductor devices under circumstances at high temperatures, relative to die attach pastes which have been used in the past.